| Timing | Timing Definition | Abbreviations | What is does |
| 2 | CAS Latency | CL | Delay between activation of row and reading of row. |
| 3 | RAS to CAS (or Row to Column Delay) | trcd | Activates row. |
| 4 | Row Precharge Delay (or RAS Precharge Delay) | trp or tRCP | Deactivates row. |
| 7 | Row Active Delay (or RAS Active Delay, or time to ready) | tra or trd or tRAS | Number of clock cycles between activation and deactivation of row. |
| 1 | Command Rate | CMD Rate | Delay between chip select and command. |
CAS latency:
CAS Latency is the ratio of the memory's column access time divided by the current system clock. The column access time turns out to be a constant value, so you can see as you in increase the system clock it becomes harder to achieve a lower CAS latency (e.g., the denominator grows, but the numerator stays the same).
RAS-to-CAS:
This is the latency between the Row Address Strobe and Column Address Strobe. Basically the delay between accessing the Row and the Column memory addresses.
Row Precharge Delay:
The number of clock cycles taken between the issuing of the precharge command and the active command. In this times the sense amps charge and the bank is activated.
Row Active Delay:
The number of clock cycles taken between a bank active command and issuing the precharge command.
Command Rate:
This is the time (here time being a clock cycle delay again) it takes the chipset to translate a virtual memory address into a physical memory address.
*From the examples above you can conclude; the lower the number, the faster the access.
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