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Ultimate Memory Guide
OTHER MEMORY TECHNOLOGIES YOU MAY
HAVE HEARD ABOUT
ENHANCED SDRAM (ESDRAM)
In order to increase the speed and efficiency of standard memory modules, some
manufacturers have incorporated a small amount of SRAM directly into the chip,
effectively creating an on-chip cache. ESDRAM is essentially SDRAM, plus a small
amount of SRAM cache, which allows for burst operations of up to 200MHz. Just
as with external cache memory, the goal of cache DRAM is to hold the most
frequently used data in the SRAM cache to minimize accesses to the slower DRAM.
One advantage of on-chip SRAM is that it enables a wider bus between the SRAM
and DRAM, effectively increasing the bandwidth and speed of the DRAM.
FAST CYCLE RAM (FCRAM)
FCRAM, co-developed by Toshiba and Fujitsu, is intended for specialty applications
such as high-end servers, printers, and telecommunications switching systems. It
includes memory array segmentation and internal pipelining that speed random
access and reduce power consumption.
SYNCLINK DRAM (SLDRAM)
Though considered obsolete today, SLDRAM was developed by a consortium of
DRAM manufacturers as an alternative to Rambus technology in the late 1990s.
VIRTUAL CHANNEL MEMORY (VCM)
Developed by NEC, VCM allows different "blocks" of memory to interface inde-pendently
with the memory controller, each with its own buffer. This way, different
system tasks can be assigned their own "virtual channels," and information related to
one function does not share buffer space with other tasks occurring at the same time,
making operations more efficient.
ERROR CHECKING
Ensuring the integrity of data stored in memory is an important aspect of memory
design. Two primary means of accomplishing this are parity and
error correction code (ECC).
Historically, parity has been the most commonly used data integrity method.
Parity can detect - but not correct - single-bit errors. Error Correction Code (ECC)
is a more comprehensive method of data integrity checking that can detect and correct
single-bit errors.
Fewer and fewer PC manufacturers are supporting data integrity checking in their
designs. This is due to a couple of factors. First, by eliminating support for parity
memory, which is more expensive than standard memory, manufacturers can lower the
price of their computers. Fortunately, this trend is complemented by the second
factor: that is, the increased quality of memory components available from certain
manufacturers and, as a result, the relative infrequency of memory errors.
The type of data integrity checking depends on how a given computer system will
be used. If the computer is to play a critical role - as a server, for example - then a
computer that supports data integrity checking is an ideal choice. In general:
- Most computers designed for use as high-end servers support ECC memory.
- Most low-cost computers designed for use at home or for small businesses support non-parity memory.
PARITY
When parity is in use on a computer system, one parity bit is stored in DRAM along
with every 8 bits (1 byte) of data. The two types of parity protocol - odd parity and
even parity - function in similar ways.
With normal parity, when 8 bits of data are written to DRAM, a corresponding parity
bit is written at the same time. The value of the parity bit (either a 1 or 0) is
determined at the time the byte is written to DRAM, based on an odd or even quantity
of 1s. Some manufacturers use a less expensive "fake parity" chip. This chip simply
generates a 1 or a 0 at the time the data is being sent to the CPU in order to
accommodate the memory controller. (For example, if the computer uses odd parity, the
fake parity chip will generate a 1 when a byte of data containing an even number of 1s
is sent to the CPU. If the byte contains an odd number of 1s, the fake parity chip
will generate a 0.) The issue here is that the fake parity chip sends an "OK" signal
no matter what. This way, it "fools" a computer that's expecting the parity bit into
thinking that parity checking is actually taking place when it is not. The bottom
line: fake parity cannot detect an invalid data bit.
This table shows how odd parity and even parity work. The processes are identical
but with opposite attributes.
| ODD PARITY |
EVEN PARITY |
| Step 1 |
The parity bit will be forced to 1 (or turned "on") if its corresponding byte of data contains an even number of 1's. |
The parity bit is forced to 0 if the byte contains an even number of 1's. |
|
If the byte contains an odd number of 1's, the parity bit is forced to 0 (or turned "off "). |
The parity bit is forced to 1 if its corresponding byte of data contains an odd number of 1's. |
|
| Step 2 |
The parity bit and the corresponding 8 bits of data are written to DRAM. |
(Same as for odd parity) |
|
| Step 3 |
Just before the data is sent to the CPU, it is intercepted by the parity circuit. |
(Same as for odd parity) |
|
If the parity circuit sees an odd number of 1's, the data is considered
valid. The parity bit is stripped from the data and the 8 data bits are passed on to the CPU. |
Data is considered valid if the parity circuit detects an even number of 1's. |
|
If the parity circuit detects an even number of 1's, the data is considered invalid and a parity error is generated. |
Data is invalid if the parity circuit detects an odd number of 1's. |
|
Parity does have its limitations. For example, parity can detect errors but cannot
make corrections. This is because the parity technology can't determine which of
the 8 data bits are invalid.
Furthermore, if multiple bits are invalid, the parity circuit will not detect the problem
if the data matches the odd or even parity condition that the parity circuit is checking
for. For example, if a valid 0 becomes an invalid 1 and a valid 1 becomes an invalid
0, the two defective bits cancel each other out and the parity circuit misses the resulting
errors. Fortunately, the chances of this happening are extremely remote.
ECC
Error Correction Code is the data integrity checking method used primarily in high-end PCs
and file servers. The important difference between ECC and parity is that ECC is capable of
detecting and correcting 1-bit errors. With ECC, 1-bit error correction usually takes place
without the user even knowing an error has occurred. Depending on the type of memory controller
the computer uses, ECC can also detect rare 2 bit memory errors. While ECC can detect a
multiple-bit errors, it cannot correct them. However, there are some more complex forms of
ECC that can correct multiple bit errors.
Using a special mathematical sequence, algorithm, and working in conjunction with the memory
controller, the ECC circuit appends ECC bits to the data bits, which are stored together in
memory. When the CPU requests data from memory, the memory controller decodes the ECC bits and
determines if one or more of the data bits are corrupted. If there's a single-bit error, the ECC
circuit corrects the bit. In the rare case of a multiple-bit error, the ECC circuit reports a
parity error.
Memory Scrubbing
Memory scrubbing is a feature initially implemented by most major server OEMs when ECC DIMMs
first became available. Memory scrubbing refers to a process that actively reads memory during
idle periods to search for and correct errors in memory. Therefore, the entire memory subsystem
would be periodically checked and cleansed as the scrubbing process repeated itself over and
over. If non-correctable memory errors are found the server management system would be alerted
as to which DIMM was causing the errors.
Chipkill
Chipkill is a highly advanced error correction method much more effective than standard ECC
correction. Chipkill provides error correction for up to four bits per DIMM. If too many
memory errors are detected chipkill technology can take the inoperative chip offline while
the server is still running to keep more errors from occurring. Chipkill support is provided
in the memory controller and implemented using standard ECC DIMMs, so it is transparent to the OS.
OTHER SPECIFICATIONS
In addition to form factors, memory technologies, and error checking methods, there
are several other specifications important to understanding and selecting memory
products.
SPEED
The speed of memory components and modules is one of the most important
factors in optimizing a memory configuration. In fact, all computer systems specify
a memory component speed. Ensuring memory compatibility requires conforming
to this specification. This section covers three measurements of memory component
and module speed: access time, megahertz, and bytes per second.
ACCESS TIME
Prior to SDRAM, memory speed was expressed by access time, measured in
nanoseconds (ns). A memory module's access time indicates the amount of time it
takes the module to deliver on a data request. So, smaller numbers indicate faster
access times. Typical speeds were 80ns, 70ns, and 60ns. Very often, you can identify
the speed of a module by the part number on the chip: such part numbers end in
"-6" for 60ns, "-7" for 70ns, and so on.
In most cases you can conform to a computer system's memory specification with
a module rated at the required speed or faster. For example, if your system requires
70ns memory, you can use both 70ns and 60ns memory without a problem.
However, some older systems check the module ID for the rated speed at system-boot
up, and will only boot up if they recognize the exact speed they are looking
for. If the system has an 80ns speed specification, for example, it won't accept
anything different than 80ns, even if it is faster. In many cases, modules could still
be built for these systems with faster memory chips on them, but the ID on the
module would be set at the slower speed to insure compatibility with the system.
This is why you can't always be sure of the rated speed on a module by looking at
the speed markings on the memory chips.
MEGAHERTZ
Beginning with the development of SDRAM technology, memory module speed has
been measured in megahertz (MHz). Speed markings on the memory chips them-selves
are typically still in nanoseconds. This can be confusing, especially since
these nanosecond markings no longer measure access time, but instead measure
the number of nanoseconds between clock cycles. For SDRAM chips with speeds
of 66MHz, 100MHz, and 133MHz, for example, the corresponding marking on the
chips are -15, -10, and -8, respectively.
This table shows the method for determining speed equivalencies between MHz and
ns ratings.
| STEP 1 |
STEP 2 |
STEP 3 |
STEP 4 |
| MHz = 1 million clock cycles per second |
Multiply by 1 million to get total clock cycles per second |
Constant: 1 billion nanoseconds per second |
Divide nanoseconds per second (from Step 3) by clock cycles per second (from Step 2) to get nanoseconds per clock cycle |
| 66 |
66,000,000 |
1,000,000,000 |
15 |
| 100 |
100,000,000 |
1,000,000,000 |
10 |
| 133 |
133,000,000 |
1,000,000,000 |
7.5 |
| nanoseconds per second |
|
1,000,000,000ns |
|
nanoseconds |
|
= |
|
= |
|
| clock cycles per second |
|
clock cycles |
|
clock cycle |
As noted in a previous section, the speed of the processor and the speed of the memory
bus are normally not the same. The speed of memory is limited by the speed of the memory
bus, which is the slowest link in the process.
BYTES PER SECOND
Converting MHz to bytes per second can be confusing at first. The two most important
pieces of information you need to make the conversion is the speed (in MHz) and the
width (in bits) of the bus.
Bus Width: If you have an 8-bit bus, then 8 bits, or 1 byte of information at a time can
travel on the bus. If you have a 64-bit bus, then 64-bits, or 8 bytes of information can
travel at a time.
Bus Speed: If the memory bus speed is 100MHz, this measures 100 million clock
cycles per second. Typically, one packet of information can travel on each clock
cycle. If the 100MHz bus is 1 byte wide, then data can travel at 100 megabytes per
second. Data travels on a 100MHz, 64-bit bus at 800 megabytes per second.
Rambus modules are sometimes measured in MHz and sometimes measured in
megabytes per second. One type of Rambus module runs on a 400MHz bus, but
because Rambus modules can send two pieces of information per clock cycle
instead of one, the module is rated at 800MHz. This is sometimes referred to as
PC-800. Because the Rambus bus width is 16-bit, or 2 bytes wide, data travels at
1600MB per second, or 1.6GB per second. Using the same logic, PC-600 Rambus
transfers data at 1.2 gigabytes per second.
REGISTERS AND BUFFERS
Registers and buffers improve memory operation by "re-driving" control signals in
the memory chips. They can be external to the memory module, or they can be
located on the module itself. Having registers and buffers placed directly on the
memory module, enables a system to support a greater quantity of modules. So,
you're likely to find these types of modules in servers and high-end workstations.
It is important to note that when upgrading, unbuffered and buffered (or registered)
modules cannot be mixed.
Buffering (EDO and FPM): For EDO and fast page modules, the process of
re-driving the signals is called buffering. With buffering there is no loss of
performance.
Registering (SDRAM): For SDRAM, the signal driving process is called
registering. Registering is similar to buffering, except that in registering, the
data is clocked in and out of the register by the system clock. Registered modules
are slightly slower than non-registered modules, because the registering process
takes one clock cycle.
An example of a buffered and a non-buffered module. They are keyed
differently, to ensure that they can't be used in place of one another.
MULTIPLE-BANKED MODULES
A multiple-banked module allows more flexibility in type of chips used. Multiple
banking allows a memory designer to divide the module into banks, which means
it can appear to the computer system to be more than one module. This design
is equivalent to the banks of memory sockets in a computer: the system accesses
one bank of memory at a time, regardless of how many actual memory sockets
comprise a bank.
Some people confuse the terms "double-sided" and "dual-banked". To clarify: Double-
sided is a physical term meaning that chips are arranged on two sides of the memory
module. Dual-banked is an electrical term meaning that the module is divided
electrically into two memory banks.
TIN VERSUS GOLD
Memory modules are manufactured with either tin leads (connectors) or gold leads.
Gold is a better conductor than tin. However, because tin is much less expensive
than gold, computer manufacturers began using tin sockets on system boards in the
early 1990s to reduce their costs. If you're buying memory and you have a choice
- that is, compatible modules come in both tin and gold - it's best to match the
metal of the module to the metal of the socket it will be going into. Matching metals
can help avoid corrosion.
Kingston's policy has always been to match metals,
so Kingston part numbers assigned to each computer system take the socket metal into
account.
REFRESH RATES
Refresh is the process of recharging, or re-energizing, the "memory cells" in
a memory chip. Internally, computer memory is arranged as a matrix of memory cells
in rows and columns - like the squares on a checkerboard - with each column
being further divided by the I/O width of the memory chip. The entire organization
of rows and columns is called a DRAM array. DRAM is called "dynamic" RAM
because it must be refreshed, or re-energized, thousands of times each second in
order to retain data. It has to be refreshed because its memory cells are designed
around tiny capacitors that store electrical charges. These capacitors work like very
tiny batteries that lose their stored charges if they are not re-energized. Also, the
process of reading data from the memory array drains these charges, so the memory
cells must also be pre-charged before reading the data.
Cells are refreshed one row at a time (usually one row per refresh cycle).The term
refresh rate refers not to the time it takes to refresh the memory but to the
total number of rows that it takes to refresh the entire DRAM array. For example, a
refresh rate of 2K indicates that it takes 2,048 rows to refresh the array; likewise,
a 4K rate indicates 4,096 rows.
Normally, the system's memory controller initiates the refresh operation. But some
chips are able to "self refresh." This means that the DRAM chip has its own refresh
circuitry and does not require intervention from the CPU or external memory
controller. Self-refresh modules dramatically reduce power consumption and are
often used in portable computers.
CAS LATENCY
The term CAS latency refers to the number of clock cycles it takes before a column
can be addressed on the DRAM chip. Latency is a measure of delay, so a "CL2" CAS
latency factor indicates a two-clock cycle delay, and a "CL3" latency factor indicates
a three-clock cycle delay. When SDRAM chips first came out, it was difficult to produce
chips with a CAS latency factor as low as CL2. And although some specifications
called for CL2, many modules worked fine at a CAS latency factor of CL3.
HEAT SPREADERS AND HEAT SINKS
As memory components get faster, chips become more dense and more circuits get
squeezed onto smaller boards. Dissipation of excess heat becomes more of an issue.
For several years now processors have incorporated fans. Newer memory module
designs use heat sinks or heat spreaders to maintain safe operating temperatures.
SERIAL PRESENCE DETECT (SPD) AND PARALLEL PRESENCE DETECT (PPD)
When a computer system boots up, it must "detect" the configuration of the memory
modules in order to run properly. Parallel Presence Detect is the traditional method
of relaying the required information by using a number of resistors. PPD is the
method SIMMs and some DIMMs use to identify themselves. Serial Presence Detect
uses an EEPROM (Electrically Erasable Programmable Read-Only Memory) to store
information about the module.
An EEPROM chip (also known as an E2PROM) differs from an EPROM in that it does not
need to be removed from the computer to be modified. However, it does have to be
erased and reprogrammed in its entirety, not selectively. It also has a limited
lifespan - that is, the number of times it can be reprogrammed is limited.
NUMBER OF CLOCK LINES (2-CLOCK VERSUS 4-CLOCK)
SDRAM memory requires that clock lines run from the system clock to the memory
module. "2-clock" means there are two clock lines running to the module, and
"4-clock" means there are four clock lines running to the module. The first Intel
designs were 2-clock because there were only eight chips on the module. Later,
4-clock designs were developed, which allowed for fewer chips per clock line, thereby
decreasing the load on each line and enabling a quicker data interface.
VOLTAGES
Voltages on memory modules keep decreasing as memory cells in DRAMs get closer
together and heat becomes more of an issue. Most computer systems used to operate
at a standard of 5 volts. Compact notebook computers were the first to use 3.3-volt
chips. This was not only because of heat issues; since lower voltage chips use less
power, using them made it easier to prolong battery life. Now most desktops are
standardized on 3.3-volt memory as well, but this is quickly being replaced by 2.5
voltage chips as products continue to get smaller and components closer together.
COMPOSITE VERSUS NON-COMPOSITE
Composite and non-composite were terms first used by Apple Computer to explain
the difference between modules of the same capacity that used a different number
of chips. To illustrate: when the industry is transitioning from one chip density to
another, there is normally a stage where you can build, for example, a memory
module with 8 of the new density chips, or 32 of the old density chips. Apple
referred to the module using the latest technology and fewer chips as
"non-composite", and the version using earlier technology and greater number of
chips as "composite". Because 32 chips on a module can cause heat and spacing
problems, Apple would often advise customers to buy non-composite modules.
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