Although most people don't realize it, the world runs on many different types of databases, all of which have one thing in common – the need for high-performance memory to deliver data quickly and reliably.
From the time we wake up to a phone call processed by our cellular service providers’ customer record database, to our weekly electronic shopping payment being processed by the financial institutions transaction database and our late night movie matinee streaming experience serving us a database of movie recommendations based on our viewing habits, databases serve many of our daily queries and need to perform consistently fast and scale dynamically to meet customer demand. 
Serving data with consistent performance and transaction integrity is no easy task and often requires in-memory databases to serve viewing recommendations and relational data nearly instantaneously to multiple users.
In-memory databases (IMDB) rely primarily on the use of high capacity and most importantly high-performance DRAM (Dynamic Random Access Memory).
They can service a high volume of requests up to x times faster than traditional disk-bound databases and serve as the backbone in any scenario that requires fast response times when querying useful data and can be used to complement big data applications.
DDR3 SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) technology memory DIMMs (Dual In-line Memory Module) are available in different capacities and speeds. The speed of a memory module is often referred to as memory frequency and is denoted using MegaHertz (MHz).
Memory frequency does have a direct relationship with memory performance,; as the memory frequency increases, so does the memory performance.
DRAM is, however, only one piece of the pie for achieving optimal memory subsystem performance. A memory controller is needed to manage the memory subsystem and different population rules governing the memory controller will affect the frequency/speed and latency at which a memory module can be addressed .
Newer generation memory controllers are embedded into the processors for best performance but require attention as some memory controllers can only run the memory subsystem at a maximum memory bandwidth of 800MHz.
Using the Intel® Romley platforms’ available 24 DIMM (Dual Inline Memory Module) sockets connected to the Intel Xeon E5 family memory subsystem, we can gauge the sustained memory bandwidth in different memory configurations using SiSoft Sandra 2012 integrated STREAM memory benchmark with different memory channel population and memory clock speeds. 
The Intel Xeon E5 family features numerous performance improvements over the previous generation of Xeon 5500 and Xeon 5600 Server processors, including two important performance related upgrades discussed in this paper, quad channel memory addressing and support for 1600MHz (MegaHertz) DDR3 (Double Data Rate) memory speeds with faster 8GT/s (GigaTransfers per second) QuickPath Interconnect (QPI) micro-architecture that benefits the connectivity bandwidth available for the reduced latency to the memory array.