Intel® Xeon® Scalable Processor Platform (Whitley)

Intel 3rd-Generation Xeon Scalable Processor Platform “Whitley”

The 3rd-Generation Intel^® Scalable Processor Platform code-named “Whitley” featuring Ice Lake-SP targets 2P servers. This microarchitecture adds 64 lanes of PCI Express^® Gen 4 per socket to enable higher I/O bandwidth per core and supports DDR4 memory frequencies of up to 3200MT/s in 2DPC (Two DIMMs per Channel) across eight channels. This is Intel’s first server processor built on 10nm wafer technology and provides a significant boost in performance over previous server generations.

At a glance

Xeon^® Scalable Processor 3rd Generation (Ice Lake-SP)

• Supports up to 6TB (Terabytes) of memory per processor{{Footnote.N67468}}
• Supports DDR4 Registered and Load Reduced DIMMs up to 3200MT/s, equivalent to transfer rates of 25.6GB/s per module

Memory architecture

Memory architecture is based on eight channels arranged in two banks per processor. Each processor can be configured with 8 or 16 modules, depending on the motherboard layout, to achieve maximum aggregated memory bandwidth.

• 8 memory channels per processor
• Up to 2 DIMMs per channel
• Up to 16 DIMMs per processor
• Up to 32 DIMM sockets per 2P server